1. Field of the Invention
The present invention relates generally to a NanoWire Field Effect Transistor (NWFET) or a finFET in which a channel core is modified to incorporate a feature for controlling threshold voltage. More specifically, the core of the nanowire channel of the NWFET or the core of the fin of the finFET is filled with an electrode material to which can be applied a backbias voltage.
2. Description of the Related Art
A recent trend in integrated circuit (IC) design is the use of nanowire transistors. FIG. 1 shows exemplarily a conventional nanowire field effect transistor (NWFET) configuration 100, wherein the nanowire 101 serves as the channel interconnecting the source 102 and drain 103. The gate 104 serves to control conductivity of the channel nanowire 101.
As shown in FIG. 1A, a gate-all-around nanowire FET 110 has a gate structure 111 that encircles the nanowire 101, as then further covered by a doped polysilicon structure 112. An example of a gate-all-around nanowire FET is described in U.S. Pat. No. 8,173,993 to Bangsaruntip, et al., the contents of which is incorporated herein by reference.
FIG. 2 shows exemplarily a conventional finFET 200, wherein the fin 201 serves as the channel interconnecting the source 202 and drain 203, with gate 204 serving to control the channel conductivity. Unlike the fin of the finFET, the nanowire channel of the NWFET 100 is typically roughly circular in cross-sectional view and is typically supported to be above the substrate, as exemplarily shown in FIG. 1A.
To optimize chip performance and leakage, multi-Vt technology is used, wherein different devices have different Ion/Ioff due to their different Vts.
However, particularly with the miniaturization of electronic devices, as exemplified by the use of NWFETs and finFETs and using conventional fabrication methods, it is difficult to achieve multiple Vt's for NWFETs and finFETs without increasing transistor variability.
That is, as exemplarily shown in FIG. 3, the conventional planar device receives an impurity implant in a planar manner so as to achieve a uniform impurities profile 301. In contrast, in a nanowire/finFET device 310, the implantation of a channel region 311 is non-planar, so that the non-uniform impurities profile can result in transistor variability 312 at the region surrounded by the gate dielectric layer and the gate layer (G).